A) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having copper wirings and including a circuit area driven at a plurality of voltages.
B) Description of the Related Art
Non-volatile memories or flash memories having floating gates are mixedly mounted on various semiconductor devices. Data write to a flash memory is performed by channel hot electron injection (CHI). Data erase of a flash memory is performed by Fowler-Nordheim tunneling. These operations require high voltage.
Although it has been tried to lower an operation voltage of a flash memory, an approach to low voltage does not progress actually because of a difficulty in thinning a tunnel oxide film in terms of reliability.
An aluminum wiring is formed by etching an aluminum layer having upper and lower barrier metal layers, and an interlayer insulating film is formed by depositing a silicon oxide film on the aluminum layer by plasma CVD. In case of the inter metal dielectric structure having aluminum wirings, there is no concern about the time dependent deterioration of breakdown between wirings, and the wiring rules defined for a low voltage area can be applied also to a high voltage layer, allowing dense patterns.
Recent needs for high speed and low power consumption of a logic circuit have expedited lowering a power supply voltage, adopting copper wirings as multilayer wirings, adopting low dielectric constant insulating films as interlayer insulating films. Since high precision etching of a copper wiring is difficult, a copper wiring is formed by a damascene process which forms wiring trenches and/or via holes in an interlayer insulating film, buries a copper wiring layer and patterns the copper wring layer by removing an unnecessary portion thereof on the interlayer insulating film. In order to prevent copper from being diffused, a barrier metal layer is formed as an underlay of the copper layer, and after the copper wiring layer is patterned, a copper diffusion preventive insulating film such as a silicon nitride film is formed on the patterned copper wiring.
A highly integrated semiconductor device has multilayer wirings. If the semiconductor device has a plurality of circuit areas, these areas use different power supply voltages in some cases. If the wiring design rule for a circuit area using a highest power supply voltage is adopted to all integrated circuits to ensure safety, the semiconductor chip area increases. Japanese Patent Laid-open Publication No. 2003-115540 proposes to change the design rule for each of circuit areas using different power supply voltages in accordance with its voltage.
Japanese Patent Laid-open Publication No. HEI-11-307639 proposes that in a power source circuit of a semiconductor integrated circuit having a plurality of power supply lines having different pitches or a plurality of power supply lines having different potentials, a relay power source line is connected to each power source line at each potential to supply power via the relay power source line.
It has been indicated that a wiring pitch is required to be controlled in accordance with the potential applied to each wiring. Japanese Patent Laid-open Publication No. 2003-31664 proposes a design method which designs a wiring layout in accordance with a wiring pitch corresponding to a potential difference between nets of a net list obtained from wiring connection information.